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Level 3 · Protocol Reference

I²C

Two wires, one shared bus, and every chip gets an address. The bus that lets a dozen sensors, EEPROMs, and clocks all share the same two pins without stepping on each other.

Overview Logic Analyzer PulseView Quadrature UART I²C SPI Parallel
Wires (clock) + (data) + GND
ClockShared, driven by the controller
TopologyMulti-drop, addressed
Typical speed100 kHz – 3.4 MHz

A Little History

I²C — "Inter-IC," pronounced "eye-squared-C" — was designed by Philips (now NXP) in 1982 to solve a problem inside their own television sets: too many chips needed to talk to each other, and every point-to-point connection between them meant more wires and more cost. I²C's pitch was that any number of chips could share just two wires, as long as each one had its own address. It worked well enough that it quietly became one of the most widely used buses in electronics, decades later.

What It's Actually For

Short-distance, low-speed communication between chips that live on the same board — sensors, real-time clocks, EEPROMs, small displays. Its whole value proposition is wire count: two shared lines can address dozens of devices, versus needing a dedicated pair (or more) per device. The tradeoff is speed and distance — I²C is not the bus you'd choose to move a lot of data quickly, or to run a signal any real distance.

How It Works

Both lines idle HIGH, held up by pull-up resistors — devices only ever pull the lines LOW, never drive them HIGH themselves (this is what lets multiple devices share the bus safely). A transaction opens with a START condition: SDA falls while SCL is still HIGH — the one moment where SDA is allowed to change while SCL isn't toggling, which is exactly what makes it recognizable as "start," not just another data bit. The controller then clocks out a 7-bit address and a read/write bit, and the addressed device pulls SDA low for one clock to that it's listening. Data bytes follow the same pattern — 8 bits, then an ACK — until the controller ends the transaction with a STOP condition: SDA rising while SCL is HIGH.

SDA START STOP SCL 10 10 00 00 ACK 01 00 00 01 ACK addr + R/W + ACK = 0x50, write data byte + ACK = 0x41 ('A') idle, both HIGH
SDA changing while SCL is HIGH is illegal everywhere except START and STOP. That one rule is what lets a receiver unambiguously tell "here's a data bit" apart from "the transaction just began or ended." Every bit here is a concrete example: the controller addresses device 0x50 for a write (1010000 0), then sends the byte 0 1 0 0 0 0 0 1 (MSB first) = 0x41 = 'A', with an ACK after each.

On the Sniffer Board

Top view of the sniffer board with the I²C header outlined in a red box
 The I²C header is boxed in red. Pins run from pin 1 at the top: SCL, SDA, GND.

One device sits on the sniffer board's I²C bus: a small EEPROM. Its memory is split into 256-byte blocks and each block answers at its own address, so expect to see the controller talk to more than one address.

I²C header pins
PinConnects to
Logic analyzer channel D0
Logic analyzer channel D1
Logic analyzer ground clip

100 kHz standard mode. In PulseView: 4 MHz sample rate, 2 second capture (about 40× oversampling). Add the I²C decoder, assign SCL = D0 and SDA = D1 — bit rate is auto-detected from the capture.